With advances of electronification and multi-functionalization of various automotive modules, automotive control system has increasingly been electronified. In place of a conventionally-known network communication system relevant to the automotive control system, using a communication protocol such as CAN, FlexRay protocol communication has been attracting a good deal of attention in view of its high failure-proof performance and increase in transmission rate.
FlexRay protocol is used for communication based on the time-division multiple access (TDMA) system. Both of periodical data communication which transmits data in a periodical manner, and non-periodical data communication such as CAN, which activates communication depending on needs, are supported by the FlexRay protocol, thereby enabling flexible and efficient use of a communication network. Duplication (redundant configuration) of a signal line (communication channel) is also supported by the FlexRay protocol, so as to improve the failure-proof performance.
In the FlexRay protocol, a state of communication is periodically repeated according to a communication cycle CM_CYC, as illustrated in FIG. 14. The communication cycle CM_CYC is composed of a static segment ST_SEG, a dynamic segment DY_SEG, a symbol window SW, and a network idle time NIT.
The static segment ST_SEG represents a period allocated to frame communication based on the static time-division multiple access system. The periodical data communication as described in the above takes place in the static segment ST_SEG. In the static segment ST_SEG, each node transmits a communication frame (static frame) in an allocated static slot STS. Each static slot STS is a period allocated to transmission of a static frame, and has a fixed length. Also the length of the static frame is fixed. The static frame includes a synchronization frame used for establishing synchronization with the communication cycle CM_CYC.
The dynamic segment DY_SEG represents a period dynamically allocated to frame communication based on a unit of mini-slot MS. The non-periodical data communication described in the above proceeds in the dynamic segment DY_SEG. In the dynamic segment DY_SEG, a communication frame (dynamic frame), which has an ID corresponded to the value of the slot counter, is given a right of transmission, as illustrated in FIG. 14. Upon completion of transmission of a frame, the slot counter is incremented, and the right of transmission shifts to a frame which has an ID corresponded to the incremented value. If there is no frame having an ID corresponded to the value of the slot counter, the slot counter is incremented while being timed by the mini-slot MS as illustrated in the drawing, and the right of transmission of the frame shifts to the frame having the next ID.
The slot counter is used for scheduling the communication within a period of communication cycle, and is owned by the individual nodes. Each node establishes synchronization of the slot counter with the communication cycle at the head of the communication cycle, and thereafter increments the slot counter using a clock of its own. In this way, synchronization among the slot counters of the individual nodes is established. The ID is an identifier of the frame, and all frames in the network are assigned certain IDs. Also the frame ID transmitted by each node is certain thereto.
The symbol window SW represents a period used for maintenance, and the network idle time NIT represents a period for adjusting the periodicity relevant to the communication cycle.
FIG. 15 is a chart illustrating a timing of transmission relevant to the dynamic frame.
In FIG. 15, TSS (transmission start sequence) represents a signal pattern which indicates the start of transmission of frame, composed of a 3 to 15-bit low level (“L” level) pattern. FSS (frame start sequence) represents a signal pattern which indicates start of frame, composed of a 1-bit high level (“H” level) pattern. BSS (byte start sequence) represents a signal pattern which indicates start of data (8 bits), composed of a 2-bit “HL” pattern. FES (frame end sequence) represents a signal pattern which indicates end of frame, composed of a 2-bit “LH” pattern. DTS (dynamic trailing sequence) represents a signal pattern which indicate end of transmission of frame, composed of an “L” level pattern having one or more bits. DTS follows FES, and continues up to a mini-slot action point MAP of the next mini-slot MS.
As described in the above, in the dynamic segment, the frame communication takes place based on the dynamic allocation using the mini-slot MS as a unit, so that the timing relevant to the dynamic frame is set on the basis of mini-slot MS. The FlexRay protocol is, however, designed to perform no communication event at around a point of change of the mini-slot MS, considering that the individual nodes operate conforming to the clocks of their own. For this reason, the communication event starts at the mini-slot action point MAP reached after the elapse of an offset time OFS from the point of change of the mini-slot MS.
The communication event herein means the start of transmission of frame, and end of transmission of frame. Since the point of time when the transmission of dynamic frame completes varies depending on volume of data to be transmitted, so that the slot counters of the individual nodes are allowed to equally vary, by placing DTS so as to keep the signal level at “L” level up to the mini-slot action point MAP in the next mini-slot MS.
In the dynamic segment, upon recognition of the end of communication of a frame currently in process, the next node starts to transmit the dynamic frame. Since a normal dynamic frame does not output nine (data and the first bit of succeeding BSS) or more consecutive bits of “H” level, so that the end of communication of the frame currently in process may be recognized by occurrence of a consecutive 11-bit or longer period where the “H” level persists. In other words, the communication terminates when eleven or more consecutive bits of “H” level are detected.
For example, as illustrated in FIG. 16, when node A on the transmitting side terminates transmission of dynamic frame (ID=m) corresponded to a value “m” of slot counter (P31), node A fixes the communication line at the high impedance state. At this time, node B on the receiving side recognizes the state as “H” level.
When “H” level is detected over a period of eleven consecutive bits, nodes A, B cause transition to the idle (IDLE) state (P32). The detection is independently participated by each node. In the IDLE state, a frame is awaited, and reception of frame starts upon recognition of the “L” level pattern.
If the length of time corresponding to the mini-slot MS elapses in the IDLE state, each node increments value of the slot counter by one, at the point of change of mini-slot MS (P33A, P33B). In this way, a dynamic frame (ID=m+1) corresponded to value (m+1) of the slot counter is authorized for transmission, and node B starts to transmit the dynamic frame (ID=m+1) (P34).
It is now assumed that, as illustrated in FIG. 17, nodes B, C and D on the receiving side are contaminated with a noise typically detected as eleven or more consecutive bits of “H” level (SN), in the period when node A on the transmitting side is transmitting the dynamic frame (ID=m) corresponded to the value m of the slot counter. Note that, in FIG. 17, TX represents a transmitted signal, and RX represents a received signal.
In this case, nodes B, C and D cause transition to the IDLE state, despite node A is transmitting the frame, because eleven consecutive bits of “H” level were detected (P41). As a consequence, nodes B, C and D terminate reception of the frame being transmitted by node A, and are brought into wait state for frame reception.
On the other hand, node A keeps on transmitting the current frame to the end. Accordingly, nodes B, C and D detect the “L” level pattern in the frame transmitted by node A, and erroneously recognize that the next frame was received (P42). As a consequence, a frame error (decoding error) generates is judged to start from the head portion of the erroneously recognized frame, and nodes B, C and D cause transition to the IDLE wait state. In the IDLE wait state, the start of frame reception is not detected.
Detection of the start of frame reception restarts when the nodes are brought into the IDLE state, but the eleven consecutive bits of “H” level is not detected since node A keeps on transmitting the residual data of the frame, so that the IDLE wait state is maintained. Since the slot counter is freely running in the IDLE wait state, so that nodes B, C and D increment the value of the slot counter by 1, at the point of change of the mini-slot MS (P43). In this way, the dynamic frame (ID=m+1) corresponded to the value (m+1) of the slot counter is authorized for transmission, and node B then starts to transmit the dynamic frame (ID=m+1) (P44).
Similarly, upon increment of the value of the slot counter by 1 at the point of change of the mini-slot MS, node C starts to transmit the dynamic frame (ID=m+2) (P45), and node D starts to transmit the dynamic frame (ID=m+3) (P46).
In this state (for example, during the period P47 illustrated in FIG. 17), what is occurring on the network is simultaneously transmission of dynamic frames from a plurality of nodes, and consequent destruction of transmission waveform caused by collision of the frames.
Once such situation occur, the individual nodes try to establish communication respectively conforming to incorrect timing, until the timing is updated (synchronization of the slot counter) at the head of the next communication cycle. In other words, the conventional problem has been such that correct communication is kept disabled until the next communication cycle is started, if eleven or more consecutive bits of “H” level are detected by the node on the receiving side due to noise contamination during transmission of the dynamic frame from the node on the transmitting side.
Patent Document 1 below describes a device and a method of generating time slot used in a home network system making use of the home PNA protocol, and discloses a technique of generating time slot using carrier sensing signal CS. For example, the document discloses control of generation of time slot, by judging presence of error in the carrier sensing signal CS.
Patent Document 2 below describes a frame synchronization device and an optical transmitter-receiver mounting the frame synchronization device. The document discloses a technique of including erroneous synchronization of the frame synchronization device, when the frame timed differently from a regular reception period is received, by determining whether the synchronization be established according to that frame, or according to the previous timing of reception.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2003-318911
Patent Document 2: Japanese Laid-Open Patent Publication No. 2005-175614